1. Field of the Invention
The present invention relates to integrated circuits including test mode circuitry and methods for testing such integrated circuits. More specifically, the inventive method is a method for testing an integrated circuit (“chip”) in which test data are sent to or from (or both to and from) the chip via one pin, the pin is also used in a normal operating mode to assert at least one signal to or from the chip, and the pin is optionally also used in a third mode (or in the test mode) for sending signals to circuitry of the chip for trimming or reconfiguring the chip.
2. Description of the Related Art
The quest to produce integrated circuits that operate with higher accuracy has led to a need for testing and final adjustment (e.g., at the manufacturing facility) of the performance of manufactured chips. Various methods have been used to improve performance of chips after they have been manufactured, including various trimming techniques that are well known in the art (such as those using laser or current trimmable resistors or zener zapping). However, prior art trimming techniques are traditionally very expensive to implement and add to the cost of the electronic system.
Also, some chips are designed to be reconfigurable to perform selected ones of multiple analog or digital (or analog and digital) functions. Such chips are useful for a range of applications, but must be designed to receive signals which can reconfigure them into different modes of operation.
To reduce the cost and complexity of chips that can be reconfigured, or tested and trimmed (or otherwise modified) after manufacture, the inventors have recognized that it would be desirable to configure them with a reduced number of pins. In accordance with the present invention, one external node of a chip (to which a single pin can be connected) is used for different purposes in different operating modes of the chip. In a test mode of the chip, test data (e.g., data for use in testing, trimming or reconfiguring the chip, or resulting from such testing, trimming or reconfiguration) are sent to or from (or both to and from) the chip via the external node. The same external node is also used in a normal operating mode of the chip, by asserting at least one signal (e.g., an enable signal) to the external node from a device external to the chip.
Throughout this disclosure, including in the claims, the expression “test mode” operation of a chip is used in a broad sense to denote an operation in which circuitry of the chip is trimmed (or otherwise configured or reconfigured) or tested. Throughout the specification (including in the claims), the expression “test data” is used in a broad sense to denote a signal (or signals) asserted to a chip to trigger (or accomplish) test mode operation of the chip, or a signal (or signals) asserted by the chip (to an external device) during test mode operation. Examples of test data include a stream of binary data (that selects one of a number of different test modes), a high voltage (for programming an EEPROM) during a test mode, a stream of binary data indicative of at least one characteristic of the chip measured during a test mode, and an analog signal indicative of at least one characteristic of the chip measured during a test mode.
Throughout this disclosure, including in the claims, the expression “external node” (or “external node”) denotes a node of a chip at which a conductor (e.g., an input pin, output pin, or input/output pin) can be connected so that a signal can be asserted from an external device via the conductor to the external node (or from internal circuitry of the chip to an external device, via the external node and the conductor) during operation of the chip. For example, Node A of FIG. 1 is an external node. The expression “internal node” denotes a node of a chip that is not an external node.